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?2010 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN6921ML " Rev. 1.0.3
4
Marking Information
1
  - Fairchild Logo
Z - Plant Code
X - Year Code (1 Digit for SOP, 2 Digits for DIP)
Y - W eek Code (1 Digit for SOP, 2 Digits for DIP)
TT   DIe-Run Code
F - Frequency (M=Low, H=High Level)
O - OLP Mode (L=Latch, R=Recovery)
T - Package Type (N=DIP, M=SOP)
P   Y=Green Package
M - Manufacture Flow Code
16
ZXYTT
FAN6921FO
TPM
 
Figure 3.   Marking Diagram
 
Pin Configuration
G N D
D E T
F B
R T
V IN
Z C D
N .C .
H V
O P W M
V D D
O P F C
C S P W M
C S P F C
IN V
C O M P
R A N G E
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
 
Figure 4.   Pin Configuration
 
Pin Definitions
Pin #   Name   Description
1
RANGE
RANGE pins impedance changes according to VIN pin voltage level. When the input voltage
etected by the VIN pin is lower than a threshold voltage, it sets to high impedance; whereas it
ets to low impedance if input voltage is high level.
2
COMP
utput pin of the error amplifier. It is a transconductance type error amplifier for PFC output
oltage feedback. Proprietary multi-vector current is built-in to this amplifier; therefore, the
ompensation for the PFC voltage feedback loop allows a simple compensation circuit between
his pin and GND.
3
INV
Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage
ivider and provides PFC output over- and under-voltage protections.
4
CSPFC
Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting
protection. When the sensed voltage across the PFC current-sensing resistor reaches the internal
hreshold (0.6 typical), the PFC switch is turned off to activate cycle-by-cycle current limiting.
5
CSPWM
Input to the comparator of the PWM over-current protection and performs PWM current-mode
ontrol with FB pin voltage. A resistor is used to sense the switching current of the PWM switch
nd the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, current-
mode control, and high / low line over-power compensation according to DET pin source current
uring PWM on time.
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